1. Field of the Invention
The present invention relates generally to a system and method for evaluation of integrated circuits and other semiconductor devices. More particularly, it relates a system incorporating hardware and suitable interconnections which allow efficient burn-in testing of a multiplicity of semiconductor devices while still incorporated in a semiconductor wafer. This invention is related to the inventions in commonly owned U.S. Pat. No. 5,429,510, issued to Barraclough et al. on Jul. 5, 1995, entitled “High-Density Interconnect Technique,” and commonly owned U.S. Pat. No. 5,682,472, issued to Brehm et al. on Oct. 28, 1997 and entitled “Method and System for Testing Memory Programming Devices,” the disclosures of which are hereby incorporated by reference herein. This invention is further related to the invention in a concurrently filed, copending, commonly owned application filed in the names of Frank 0. Uher. Mark C. Carbone, John W. Andberg and Donald P. Richmond II, entitled “Wafer Level Burn-In and Test Cartridge”, the disclosure of which is also incorporated by reference herein.
2. Description of the Prior Art
When fabrication of integrated circuits and other semiconductor devices has been completed, the semiconductor devices are subjected to burn-in and electrical tests in order to identify and eliminate defective semiconductor devices before shipment to a customer. The term “burn-in” relates to operation of an integrated circuit at a predetermined temperature or temperature profile, typically an elevated temperature in an oven, a reduced temperature in an environmentally controlled enclosure, or a combination of an elevated temperature followed by a reduced temperature. Certain operating electrical bias levels and/or signals are supplied to the semiconductor devices while they are at the elevated temperature. The use of the elevated temperature or the combination of an elevated temperature followed by a reduced temperature accelerates stress to which the devices are subjected during burn-in, so that marginal devices that would otherwise fail shortly after being placed in service fail during burn-in and are eliminated before shipping. In electrical test, a more complete set of operating electrical bias levels and signals are supplied to the device to provide a thorough evaluation of its functions.
As is apparent from the Brehm et al. patent, there are a variety of bum in and electrical test systems known in the art for burn-in and electrical test of integrated circuits and other semiconductor devices. To date, most of the prior art systems carry out the burn-in and electrical test after the integrated circuits have been separated into individual chips or die from a wafer in which they have been manufactured.
More recently, interest has developed in wafer-level burn-in systems, some of which systems also include electrical test capability. In these systems, the integrated circuits undergo burn-in and may undergo electrical test prior to separation into individual integrated circuit chips.
Wafer-level burn-in systems have attracted interest because they allow defective integrated circuits to be identified by the burn-in process before additional expense is incurred in their handling and packaging. Similarly, it is desirable to carry out electrical test of the integrated circuits while they are still in wafer form. Electrical test involves applying a suite of electrical signal inputs to each integrated circuit to make sure that it performs properly for its intended use.
While the ability to carry out both burn-in and electrical test in a single wafer-level system is a highly desired result, there are significant interconnection, signal supply and power supply problems to be overcome before such a system can be implemented in practice. In a preferred implementation, the present invention is directed to solving those problems. In its broadest form, aspects of the present invention may, however, be employed in a system that carries out wafer-level burn-in or wafer-level electrical test alone.